786 Processors Data Chart

[ Athlon(slot A) | Athlon(socket A) | Pentium 4 (socket 423/478) | Xeon (socket 603) | Itanium(Merced) | Athlon 64(socket 754) | Opteron(socket 940) | ]

Athlon (Slot A)
AMD
Processors
Natural
State
Sockets L1/L2 Cache
(Associativity)
Transistors
Athlon-500 MMX 3DNow!
(K7)
August 9, 1999 - {$249}
575 pins (242 pin SEC)
500MHz (100x5.0)
(64-bit dual-pumped bus)
1.6v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable
22 million
0.25痠 process
184mm² die
Athlon-550 MMX 3DNow!
(K7)
August 9, 1999 - {$449}
575 pins (242 pin SEC)
550MHz (100x5.5)
(64-bit dual-pumped bus)
1.6v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable
22 million
0.25痠 process
184mm² die
Athlon-600 MMX 3DNow!
(K7)
August 9, 1999 - {$615}
575 pins (242 pin SEC)
600MHz (100x6.0)
(64-bit dual-pumped bus)
1.6v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable
22 million
0.25痠 process
184mm² die
Athlon-650 MMX 3DNow!
(K7)
August 9, 1999 - {$849}
575 pins (242 pin SEC)
650MHz (100x6.5)
(64-bit dual-pumped bus)
1.6v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable
22 million
0.25痠 process
184mm² die
Athlon-700 MMX 3DNow!
(K7)
October 4, 1999 - {$849}
575 pins (242 pin SEC)
700MHz (100x7.0)
(64-bit dual-pumped bus)
1.6v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable
22 million
0.25痠 process
184mm² die
Athlon-550 MMX 3DNow!
(K75)
January 2000
575 pins (242 pin SEC)
550MHz (100x5.5)
(64-bit dual-pumped bus)
1.6v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable
22 million
0.18痠 process
102mm² die
Athlon-600 MMX 3DNow!
(K75)
January 2000
575 pins (242 pin SEC)
600MHz (100x6.0)
(64-bit dual-pumped bus)
1.6v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable
22 million
0.18痠 process
102mm² die
Athlon-650 MMX 3DNow!
(K75)
January 2000
575 pins (242 pin SEC)
650MHz (100x6.5)
(64-bit dual-pumped bus)
1.6v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable
22 million
0.18痠 process
102mm² die
Athlon-700 MMX 3DNow!
(K75)
January 2000
575 pins (242 pin SEC)
700MHz (100x7.0)
(64-bit dual-pumped bus)
1.6v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2 speed) (2-way)
* 64GB cacheable
22 million
0.18痠 process
102mm² die
Athlon-750 MMX 3DNow!
(K75)
November 29, 1999 - {$799}
575 pins (242 pin SEC)
750MHz (100x7.5)
(64-bit dual-pumped bus)
1.6v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2.5 speed) (2-way)
* 64GB cacheable
22 million
0.18痠 process
102mm² die
Athlon-800 MMX 3DNow!
(K75)
January 6, 2000 - {$849}
575 pins (242 pin SEC)
800MHz (100x8.0)
(64-bit dual-pumped bus)
1.7v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2.5 speed) (2-way)
* 64GB cacheable
22 million
0.18痠 process
102mm² die
Athlon-850 MMX 3DNow!
(K75)
February 11, 2000 - {$849}
575 pins (242 pin SEC)
850MHz (100x8.5)
(64-bit dual-pumped bus)
1.7v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/2.5 speed) (2-way)
* 64GB cacheable
22 million
0.18痠 process
102mm² die
Athlon-900 MMX 3DNow!
(K75)
March 6, 2000 - {$899}
575 pins (242 pin SEC)
900MHz (100x9.0)
(64-bit dual-pumped bus)
1.8v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/3 speed) (2-way)
* 64GB cacheable
22 million
0.18痠 process
102mm² die
Athlon-950 MMX 3DNow!
(K75)
March 6, 2000 - {$999}
575 pins (242 pin SEC)
950MHz (100x9.5)
(64-bit dual-pumped bus)
1.8v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/3 speed) (2-way)
* 64GB cacheable
22 million
0.18痠 process
102mm² die
Athlon-1G MMX 3DNow!
(K75)
March 6, 2000 - {$1299}
575 pins (242 pin SEC)
1000MHz (100x10.0)
(64-bit dual-pumped bus)
1.8v/3.3v split
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB unified L2 (1/3 speed) (2-way)
* 64GB cacheable
22 million
0.18痠 process
102mm² die
Athlon-650 MMX 3DNow!
(Thunderbird)
? pins (242 pin SEC)
650MHz (100x6.5)
(64-bit dual-pumped bus)
1.7v
Slot A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-700 MMX 3DNow!
(Thunderbird)
? pins (242 pin SEC)
700MHz (100x7.0)
(64-bit dual-pumped bus)
1.7v
Slot A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-750 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$319}
? pins (242 pin SEC)
750MHz (100x7.5)
(64-bit dual-pumped bus)
1.7v
Slot A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-800 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$359}
? pins (242 pin SEC)
800MHz (100x8.0)
(64-bit dual-pumped bus)
1.7v
Slot A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-850 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$507}
? pins (242 pin SEC)
850MHz (100x8.5)
(64-bit dual-pumped bus)
1.7v
Slot A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-900 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$589}
? pins (242 pin SEC)
900MHz (100x9.0)
(64-bit dual-pumped bus)
1.75v
Slot A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-950 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$759}
? pins (242 pin SEC)
950MHz (100x9.5)
(64-bit dual-pumped bus)
1.75v
Slot A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1G MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$990}
? pins (242 pin SEC)
1000MHz (100x10.0)
(64-bit dual-pumped bus)
1.75v
Slot A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon Ultra-1.33G MMX 3DNow!
(Mustang)
[cancelled]
? pins (242 pin SEC)
1333MHz (133x10)
(64-bit dual-pumped bus)
?v
Slot A 64KB data (2-way)
64KB instruction (2-way)
512KB or
1MB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
? million
0.18痠 process
120+mm² die
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Athlon (Socket A)
AMD
Processors
Natural
State
Sockets L1/L2 Cache
(Associativity)
Transistors
Duron-600 MMX 3DNow!
(Spitfire)
June 19, 2000 - {$112}
453 pins
600MHz (100x6.0)
(64-bit dual-pumped bus)
1.5v or 1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25 million
0.18痠 process
100mm² die
Duron-650 MMX 3DNow!
(Spitfire)
June 19, 2000 - {$154}
453 pins
650MHz (100x6.5)
(64-bit dual-pumped bus)
1.5v or 1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25 million
0.18痠 process
100mm² die
Duron-700 MMX 3DNow!
(Spitfire)
June 19, 2000 - {$192}
453 pins
700MHz (100x7.0)
(64-bit dual-pumped bus)
1.5v or 1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25 million
0.18痠 process
100mm² die
Duron-750 MMX 3DNow!
(Spitfire)
September 5, 2000 - {$181}
453 pins
750MHz (100x7.5)
(64-bit dual-pumped bus)
1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25 million
0.18痠 process
100mm² die
Duron-800 MMX 3DNow!
(Spitfire)
October 17, 2000 - ($170)
453 pins
800MHz (100x8.0)
(64-bit dual-pumped bus)
1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25 million
0.18痠 process
100mm² die
Duron-850 MMX 3DNow!
(Spitfire)
January 8, 2001 - {$149}
453 pins
850MHz (100x8.5)
(64-bit dual-pumped bus)
1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25 million
0.18痠 process
100mm² die
Duron-900 MMX 3DNow!
(Spitfire)
April 2, 2001 - {$129}
453 pins
900MHz (100x9.0)
(64-bit dual-pumped bus)
1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25 million
0.18痠 process
100mm² die
Duron-950 MMX 3DNow!
(Spitfire)
June 6, 2001 - {$122}
453 pins
950MHz (100x9.5)
(64-bit dual-pumped bus)
1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25 million
0.18痠 process
100mm² die
Duron-1.0G MMX 3DNow! SSE
(Morgan)
August 20, 2001 - {$89}
453 pins
1000MHz (100x10.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25.2 million
0.18痠 process
106mm² die
Duron-1.1G MMX 3DNow! SSE
(Morgan)
October 1, 2001 - {$103}
453 pins
1100MHz (100x11.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25.2 million
0.18痠 process
106mm² die
Duron-1.2G MMX 3DNow! SSE
(Morgan)
November 15, 2001 - {$103}
453 pins
1200MHz (100x12.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25.2 million
0.18痠 process
106mm² die
Duron-1.3G MMX 3DNow! SSE
(Morgan)
January 21, 2002 - {$118}
453 pins
1300MHz (100x13.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
25.2 million
0.18痠 process
106mm² die
Duron-1.33G MMX 3DNow! SSE
(Appaloosa)
[not released]
453 pins
1333MHz (133x10.0)
(64-bit dual-pumped bus)
?v
Socket A 64KB data (2-way)
64KB instruction (2-way)
?KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
? million
0.13痠 process
?mm² die
Duron-1.4G MMX 3DNow! SSE
(Applebred)
August 2003 - {$32}
453 pins
1400MHz (133x10.5)
(64-bit dual-pumped bus)
1.5v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
? million
0.13痠 process
?mm² die
Duron-1.6G MMX 3DNow! SSE
(Applebred)
August 2003 - {$39}
453 pins
1600MHz (133x12.0)
(64-bit dual-pumped bus)
1.5v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
? million
0.13痠 process
?mm² die
Duron-1.8G MMX 3DNow! SSE
(Applebred)
August 2003 - {$47}
453 pins
1800MHz (133x13.5)
(64-bit dual-pumped bus)
1.5v
Socket A 64KB data (2-way)
64KB instruction (2-way)
64KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
? million
0.13痠 process
?mm² die
Athlon-650 MMX 3DNow!
(Thunderbird)
200x?
453 pins
650MHz (100x6.5)
(64-bit dual-pumped bus)
1.7v or 1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-700 MMX 3DNow!
(Thunderbird)
200x?
453 pins
700MHz (100x7.0)
(64-bit dual-pumped bus)
1.7v or 1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-750 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$319}
453 pins
750MHz (100x7.5)
(64-bit dual-pumped bus)
1.7v or 1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-800 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$359}
453 pins
800MHz (100x8.0)
(64-bit dual-pumped bus)
1.7v or 1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-850 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$507}
453 pins
850MHz (100x8.5)
(64-bit dual-pumped bus)
1.7v or 1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-900 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$589}
453 pins
900MHz (100x9.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-950 MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$759}
453 pins
950MHz (100x9.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1G MMX 3DNow!
(Thunderbird)
June 5, 2000 - {$990}
453 pins
1000MHz (100x10.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1G MMX 3DNow!
(Thunderbird)
October 30, 2000 - {$385}
453 pins
1000MHz (133x7.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1.1G MMX 3DNow!
(Thunderbird)
August 28, 2000 - {$853}
453 pins
1100MHz (100x11.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1.13G MMX 3DNow!
(Thunderbird)
October 30, 2000 - {$506}
453 pins
1133MHz (133x8.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1.2G MMX 3DNow!
(Thunderbird)
October 17, 2000 - {$612}
453 pins
1200MHz (100x12.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1.2G MMX 3DNow!
(Thunderbird)
October 30, 2000 - {$673}
453 pins
1200MHz (133x9.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1.3G MMX 3DNow!
(Thunderbird)
March 22, 2001 - {$318}
453 pins
1300MHz (100x13.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1.33G MMX 3DNow!
(Thunderbird)
March 22, 2001 - {$350}
453 pins
1333MHz (133x10.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1.4G MMX 3DNow!
(Thunderbird)
June 6, 2001 - {$253}
453 pins
1400MHz (100x14.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon-1.4G MMX 3DNow!
(Thunderbird)
June 6, 2001 - {$253}
453 pins
1400MHz (133x10.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37 million
0.18痠 process
120mm² die
Athlon Ultra-1.33G MMX 3DNow!
(Mustang)
[cancelled]
453 pins
1333MHz (133x10)
(64-bit dual-pumped bus)
?v
Socket A 64KB data (2-way)
64KB instruction (2-way)
512KB or
1MB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
? million
0.18痠 process
120+mm² die
Athlon MP-1.0G MMX 3DNow! SSE
(Palomino)
June 5, 2001 - {$215}
453 pins
1000MHz (133x7.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon MP-1.2G MMX 3DNow! SSE
(Palomino)
June 5, 2001 - {$265}
453 pins
1200MHz (133x9.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon MP-1500+ MMX 3DNow! SSE
(Palomino)
October 15, 2001 - {$180}
453 pins
1333MHz (133x10.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon MP-1600+ MMX 3DNow! SSE
(Palomino)
October 15, 2001 - {$210}
453 pins
1400MHz (133x10.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon MP-1800+ MMX 3DNow! SSE
(Palomino)
October 15, 2001 - {$302}
453 pins
1533MHz (133x11.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon MP-1900+ MMX 3DNow! SSE
(Palomino)
December 12, 2001 - {$319}
453 pins
1600MHz (133x12.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon MP-2000+ MMX 3DNow! SSE
(Palomino)
March 13, 2002 - {$415}
453 pins
1666MHz (133x12.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon MP-2100+ MMX 3DNow! SSE
(Palomino)
June 19, 2002 - {$262}
453 pins
1733MHz (133x13.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon MP-2000+ MMX 3DNow! SSE
(Thoroughbred)
August 27, 2002
453 pins
1666MHz (133x12.5)
(64-bit dual-pumped bus)
1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
85mm² die
Athlon MP-2200+ MMX 3DNow! SSE
(Thoroughbred)
August 27, 2002 - {$224}
453 pins
1800MHz (133x13.5)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
85mm² die
Athlon MP-2400+ MMX 3DNow! SSE
(Thoroughbred)
December 10, 2002 - {$228}
453 pins
2000MHz (133x15.0)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
85mm² die
Athlon MP-2600+ MMX 3DNow! SSE
(Thoroughbred)
February 4, 2003 - {$273}
453 pins
2133MHz (133x16.0)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
85mm² die
Athlon MP-2800+ MMX 3DNow! SSE
(Barton MP)
May 6, 2003 - {$275}
453 pins
2133MHz (133x16)
(64-bit dual-pumped bus)
1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
54.3 million
0.13痠 process
101mm² die
Athlon MP-??? MMX 3DNow! SSE
(Barton MP)
2003?
453 pins
?MHz (133x?)
(64-bit dual-pumped bus)
1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
54.3 million
0.13痠 process
101mm² die
Athlon XP-1500+ MMX 3DNow! SSE
(Palomino)
October 9, 2001 - {$130}
453 pins
1333MHz (133x10.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon XP-1600+ MMX 3DNow! SSE
(Palomino)
October 9, 2001 - {$160}
453 pins
1400MHz (133x10.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon XP-1700+ MMX 3DNow! SSE
(Palomino)
October 9, 2001 - {$190}
453 pins
1466MHz (133x11.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon XP-1800+ MMX 3DNow! SSE
(Palomino)
October 9, 2001 - {$252}
453 pins
1533MHz (133x11.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon XP-1900+ MMX 3DNow! SSE
(Palomino)
November 5, 2001 - {$269}
453 pins
1600MHz (133x12.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon XP-2000+ MMX 3DNow! SSE
(Palomino)
January 7, 2002 - {$339}
453 pins
1666MHz (133x12.5)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon XP-2100+ MMX 3DNow! SSE
(Palomino)
March 13, 2002 - {$420}
453 pins
1733MHz (133x13.0)
(64-bit dual-pumped bus)
1.75v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.5 million
0.18痠 process
128mm² die
Athlon XP-1600+ MMX 3DNow! SSE
(Thoroughbred)
May, 2003
453 pins
1400MHz (133x10.5)
(64-bit dual-pumped bus)
1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
81mm² die
84mm² die (Dec 02)
Athlon XP-1700+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002
453 pins
1466MHz (133x11.0)
(64-bit dual-pumped bus)
1.5v or 1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
81mm² die
84mm² die (Dec 02)
Athlon XP-1800+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002
453 pins
1533MHz (133x11.5)
(64-bit dual-pumped bus)
1.5v or 1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
81mm² die
84mm² die (Dec 02)
Athlon XP-1900+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002
453 pins
1600MHz (133x12.0)
(64-bit dual-pumped bus)
1.5v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
81mm² die
Athlon XP-2000+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002
453 pins
1666MHz (133x12.5)
(64-bit dual-pumped bus)
1.6v or 1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
81mm² die
84mm² die (Dec 02)
Athlon XP-2100+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002
453 pins
1733MHz (133x13.0)
(64-bit dual-pumped bus)
1.6v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
81mm² die
Athlon XP-2200+ MMX 3DNow! SSE
(Thoroughbred)
June 10, 2002 - {$241}
453 pins
1800MHz (133x13.5)
(64-bit dual-pumped bus)
1.6v or 1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
81mm² die
84mm² die (Dec 02)
Athlon XP-2400+ MMX 3DNow! SSE
(Thoroughbred)
August 21, 2002 - {$193}
453 pins
2000MHz (133x15.0)
(64-bit dual-pumped bus)
1.6v or 1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
84mm² die
Athlon XP-2600+ MMX 3DNow! SSE
(Thoroughbred)
August 21, 2002 - {$297}
453 pins
2133MHz (133x16.0)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
84mm² die
Athlon XP-2600+ MMX 3DNow! SSE
(Thoroughbred)
November, 2002
453 pins
2083MHz (166x12.5)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
84mm² die
Athlon XP-2700+ MMX 3DNow! SSE
(Thoroughbred)
November, 2002 - {$349}
453 pins
2166MHz (166x13.0)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
84mm² die
Athlon XP-2800+ MMX 3DNow! SSE
(Thoroughbred)
November, 2002 - {$397}
453 pins
2250MHz (166x13.5)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
37.2 million
0.13痠 process
84mm² die
Athlon XP-2500+ MMX 3DNow! SSE
(Barton)
February 10, 2003
453 pins
1833MHz (166x11.0)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
54.3 million
0.13痠 process
101mm² die
Athlon XP-2600+ MMX 3DNow! SSE
(Barton)
May 13, 2003
453 pins
1916MHz (166x11.5)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
54.3 million
0.13痠 process
101mm² die
Athlon XP-2800+ MMX 3DNow! SSE
(Barton)
February 10, 2003
453 pins
2083MHz (166x12.5)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
54.3 million
0.13痠 process
101mm² die
Athlon XP-3000+ MMX 3DNow! SSE
(Barton)
February 10, 2003 - {$588}
453 pins
2166MHz (166x13.0)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
54.3 million
0.13痠 process
101mm² die
Athlon XP-3000+ MMX 3DNow! SSE
(Barton)
May 13, 2003
453 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
54.3 million
0.13痠 process
101mm² die
Athlon XP-3200+ MMX 3DNow! SSE
(Barton)
2003?
453 pins
?MHz (166x?)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
54.3 million
0.13痠 process
101mm² die
Athlon XP-3200+ MMX 3DNow! SSE
(Barton)
May 13, 2003 - {$464}
453 pins
2200MHz (200x11.0)
(64-bit dual-pumped bus)
1.65v
Socket A 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
54.3 million
0.13痠 process
101mm² die
Athlon XP-??? MMX 3DNow! SSE
(Thoroughbred-S)
2003?
453 pins
?MHz (?x?)
(64-bit dual-pumped bus)
?v
Socket A 64KB data (2-way)
64KB instruction (2-way)
?KB on-Die unified L2 (16-way exclusive)
* 64GB cacheable
? million
0.09痠 process
50mm² die
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Pentium 4 (Socket 423/478)
Intel
Processors
Natural
State
Sockets L1/L2 Cache
(Associativity)
Transistors
Pentium 4-1.3G MMX SSE SSE2
(Willamette)
January 3, 2001 - {$409}
423 pins
1300MHz (100x13)
(64-bit quad-pumped bus)
1.7v or 1.75v
Socket 423 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.4G MMX SSE SSE2
(Willamette)
November 20, 2000 - {$644}
423 pins
1400MHz (100x14)
(64-bit quad-pumped bus)
1.7v or 1.75v
Socket 423 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.5G MMX SSE SSE2
(Willamette)
November 20, 2000 - {$819}
423 pins
1500MHz (100x15)
(64-bit quad-pumped bus)
1.7v or 1.75v
Socket 423 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.6G MMX SSE SSE2
(Willamette)
July 2, 2001 - {$294}
423 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.75v
Socket 423 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.7G MMX SSE SSE2
(Willamette)
April 23, 2001 - {$352}
423 pins
1700MHz (100x17)
(64-bit quad-pumped bus)
1.75v
Socket 423 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.8G MMX SSE SSE2
(Willamette)
July 2, 2001 - {$562}
423 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.75v
Socket 423 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.9G MMX SSE SSE2
(Willamette)
August 27, 2001 - {$375}
423 pins
1900MHz (100x19)
(64-bit quad-pumped bus)
1.75v
Socket 423 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-2.0G MMX SSE SSE2
(Willamette)
August 27, 2001 - {$562}
423 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.75v
Socket 423 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.4G MMX SSE SSE2
(Willamette)
September 27, 2001
478 pins
1400MHz (100x14)
(64-bit quad-pumped bus)
1.75v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.5G MMX SSE SSE2
(Willamette)
August 27, 2001
478 pins
1500MHz (100x15)
(64-bit quad-pumped bus)
1.75v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.6G MMX SSE SSE2
(Willamette)
August 27, 2001
478 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.75v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.7G MMX SSE SSE2
(Willamette)
August 27, 2001
478 pins
1700MHz (100x17)
(64-bit quad-pumped bus)
1.75v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.8G MMX SSE SSE2
(Willamette)
August 27, 2001
478 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.75v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.9G MMX SSE SSE2
(Willamette)
August 27, 2001 - {$375}
478 pins
1900MHz (100x19)
(64-bit quad-pumped bus)
1.75v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-2.0G MMX SSE SSE2
(Willamette)
August 27, 2001 - {$562}
478 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.75v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Pentium 4-1.6A MMX SSE SSE2
(Northwood)
(Low wattage chip)
January 7, 2002
478 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.5v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (Jul 02)
Pentium 4-1.8A MMX SSE SSE2
(Northwood)
(Low wattage chip)
January 7, 2002
478 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.5v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (Jul 02)
Pentium 4-2.0A MMX SSE SSE2
(Northwood)
(Low wattage chip)
January 7, 2002
478 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.5v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (Jul 02)
Pentium 4-1.6A MMX SSE SSE2
(Northwood)
January 7, 2002
478 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.5v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (Jul 02)
Pentium 4-1.8A MMX SSE SSE2
(Northwood)
January 7, 2002
478 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.5v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (Jul 02)
Pentium 4-2.0A MMX SSE SSE2
(Northwood)
January 7, 2002 - {$364}
478 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (Jul 02)
Pentium 4-2.2G MMX SSE SSE2
(Northwood)
January 7, 2002 - {$562}
478 pins
2200MHz (100x22)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (Jul 02)
Pentium 4-2.26G MMX SSE SSE2
(Northwood)
May 5, 2002 - {$423}
478 pins
2266MHz (133x17)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (Jul 02)
Pentium 4-2.4G MMX SSE SSE2
(Northwood)
April 2, 2002 - {$562}
478 pins
2400MHz (100x24)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (Jul 02)
Pentium 4-2.4B MMX SSE SSE2
(Northwood)
May 5, 2002 - {$562}
478 pins
2400MHz (133x18)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (Jul 02)
Pentium 4-2.4C MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading Technology)
May 21, 2003 - {$178}
478 pins
2400MHz (200x12)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Pentium 4-2.5G MMX SSE SSE2
(Northwood)
August 26, 2002 - {$243}
478 pins
2500MHz (100x25)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Pentium 4-2.53G MMX SSE SSE2
(Northwood)
May 5, 2002 - {$637}
478 pins
2533MHz (133x19)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
146mm² die
131mm² die (May 02)
Pentium 4-2.6G MMX SSE SSE2
(Northwood)
August 26, 2002 - {$401}
478 pins
2600MHz (100x26)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Pentium 4-2.6C MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading Technology)
May 21, 2003 - {$218}
478 pins
2600MHz (200x13)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Pentium 4-2.67G MMX SSE SSE2
(Northwood)
August 26, 2002 - {$401}
478 pins
2666MHz (133x20)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Pentium 4-2.8G MMX SSE SSE2
(Northwood)
August 26, 2002 - {$508}
478 pins
2800MHz (133x21)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Pentium 4-2.8C MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading Technology)
May 21, 2003 - {$278}
478 pins
2800MHz (200x14)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Pentium 4-3.0G MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading Technology)
April 14, 2003 - {$417}
478 pins
3000MHz (200x15)
(64-bit quad-pumped bus)
1.475v or 1.5v or
1.525 or 1.55v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Pentium 4-3.06G MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading Technology)
November 14, 2002 - {$637}
478 pins
3066MHz (133x23)
(64-bit quad-pumped bus)
1.475v or 1.5v or
1.525v or 1.55v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Pentium 4-3.2C MMX SSE SSE2
(Northwood)
(Jackson Hyperthreading Technology)
June 23, 2003 - {$637}
478 pins
3200MHz (200x16)
(64-bit quad-pumped bus)
1.475v or 1.5v or
1.525v or 1.55v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Pentium 4 Extreme-3.2G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading Technology)
November 2003
478 pins
3200MHz (200x16)
(64-bit quad-pumped bus)
1.475v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable
169 million
0.13痠 process
~230mm² die
Pentium 4-2.4G MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading Technology)
2H 2003?
775 balls
2400MHz (200x12)
(64-bit quad-pumped bus)
?v
Socket T 16KB data (4-way)
16k 發ps trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable
? million
0.09痠 process
81mm² die
Pentium 4-3.6G MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading Technology)
1Q 2004?
775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
?v
Socket T 16KB data (4-way)
16k 發ps trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable
? million
0.09痠 process
81mm² die
Pentium 4-3.8G MMX SSE SSE2 SSE3
(Prescott)
(Jackson Hyperthreading Technology)
2Q 2004?
775 balls
3800MHz (200x19)
(64-bit quad-pumped bus)
?v
Socket T 16KB data (4-way)
16k 發ps trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable
? million
0.09痠 process
81mm² die
Pentium 4-3.6G MMX SSE SSE2 SSE3
(Tejas)
(Jackson Hyperthreading Technology)
2H 2004?
775 balls
3600MHz (200x18)
(64-bit quad-pumped bus)
?v
Socket T 24KB data (4-way)
16k 發ps trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable
? million
0.09痠 process
?mm² die
Pentium 4-??? MMX SSE SSE2 SSE3
(Tejas)
(Jackson Hyperthreading Technology)
2004?
775 balls
?MHz (266x?)
(64-bit quad-pumped bus)
?v
Socket T 24KB data (4-way)
16k 發ps trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable
? million
0.09痠 process
?mm² die
Pentium 4-??? MMX SSE SSE2 SSE3
(Nehalem)
(Jackson Hyperthreading Technology)
200x?
775 balls
?MHz (200x?)
(64-bit quad-pumped bus)
?v
Socket T ?KB data (4-way)
?k 發ps trace instruction (8-way)
?MB on-Die unified L2 (8-way)
* ?GB cacheable
? million
0.065痠 process
?mm² die
Celeron-1.7G MMX SSE SSE2
(Willamette)
May 15, 2002 - {$83}
478 pins
1700MHz (100x17)
(64-bit quad-pumped bus)
1.75v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Celeron-1.8G MMX SSE SSE2
(Willamette)
June 12, 2002 - {$103}
478 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.75v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Celeron-2.0G MMX SSE SSE2
(Northwood-128)
September 18, 2002 - {$103}
478 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Celeron-2.1G MMX SSE SSE2
(Northwood-128)
November 20, 2002 - {$89}
478 pins
2100MHz (100x21)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Celeron-2.2G MMX SSE SSE2
(Northwood-128)
November 20, 2002 - {$103}
478 pins
2200MHz (100x22)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Celeron-2.3G MMX SSE SSE2
(Northwood-128)
March 31, 2003 - {$117}
478 pins
2300MHz (100x23)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Celeron-2.4G MMX SSE SSE2
(Northwood-128)
March 31, 2003 - {$127}
478 pins
2400MHz (100x24)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Celeron-2.5G MMX SSE SSE2
(Northwood-128)
June 25, 2003 - {$89}
478 pins
2500MHz (100x25)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Celeron-2.6G MMX SSE SSE2
(Northwood-128)
June 25, 2003 - {$103}
478 pins
2600MHz (100x26)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Celeron-2.7G MMX SSE SSE2
(Northwood-128)
September 24, 2003 - {$104}
478 pins
2700MHz (100x27)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
Celeron-2.8G MMX SSE SSE2
(Northwood-128)
1Q 2004?
478 pins
2800MHz (100x28)
(64-bit quad-pumped bus)
1.475v or 1.5v or 1.525v
Socket 478 8KB data (4-way)
12k 發ps trace instruction (8-way)
128KB on-Die unified L2 (8-way)
* 4GB cacheable
55 million
0.13痠 process
131mm² die
VIA
Processors
Natural
State
Sockets L1/L2 Cache
(Associativity)
Transistors
? MMX SSE
(CZA)
2004?
478 pins
?MHz (?x?)
?v
Socket 478 ?KB data (?-way)
?KB instruction (?-way)
?KB on-Die L2
* ?GB cacheable
? million
0.10痠 process
?mm² die
Goto  Top of Page..
Xeon (Socket 603)
Intel
Processors
Natural
State
Sockets L1/L2 Cache
(Associativity)
Transistors
Xeon-1.4G MMX SSE SSE2
(Foster)
May 21, 2001 - {$268}
603 pins
1400MHz (100x14)
(64-bit quad-pumped bus)
1.7v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Xeon-1.5G MMX SSE SSE2
(Foster)
May 21, 2001 - {$309}
603 pins
1500MHz (100x15)
(64-bit quad-pumped bus)
1.7v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Xeon-1.7G MMX SSE SSE2
(Foster)
May 21, 2001 - {$406}
603 pins
1700MHz (100x17)
(64-bit quad-pumped bus)
1.7v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Xeon-2.0G MMX SSE SSE2
(Foster)
September 25, 2001 - {$615}
603 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.7v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
* 4GB cacheable
42 million
0.18痠 process
217mm² die
Xeon MP-1.4G MMX SSE SSE2
(Foster MP)
(Jackson Hyperthreading Technology)
March 12, 2002 - {$1177}
603 pins
1400MHz (100x14)
(64-bit quad-pumped bus)
1.7v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
512KB L3 (?-way)
* 64GB cacheable
108 million
0.18痠 process
?mm² die
Xeon MP-1.5G MMX SSE SSE2
(Foster MP)
(Jackson Hyperthreading Technology)
March 12, 2002 - {$1980}
603 pins
1500MHz (100x15)
(64-bit quad-pumped bus)
1.7v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
512KB L3 (?-way)
* 64GB cacheable
108 million
0.18痠 process
?mm² die
Xeon MP-1.6G MMX SSE SSE2
(Foster MP)
(Jackson Hyperthreading Technology)
March 12, 2002 - {$3692}
603 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.7v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
1MB L3 (?-way)
* 64GB cacheable
108 million
0.18痠 process
?mm² die
Xeon MP-1.7G MMX SSE SSE2
(Foster MP)
(Jackson Hyperthreading Technology)
[not released]
603 pins
1700MHz (100x17)
(64-bit quad-pumped bus)
1.7v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
256KB on-Die unified L2 (8-way)
1MB L3 (?-way)
* 64GB cacheable
108 million
0.18痠 process
?mm² die
LV Xeon-1.6G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
September 3, 2002 - {$355}
604 pins
1600MHz (100x16)
(64-bit quad-pumped bus)
1.3v
Socket 604 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
146mm² die
Xeon-1.8G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
February 25, 2002 - {$251}
603 pins
1800MHz (100x18)
(64-bit quad-pumped bus)
1.5v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
146mm² die
Xeon-2.0A MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
February 25, 2002 - {$417}
603 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.5v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
146mm² die
LV Xeon-2.0A MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
April, 2003
604 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.3v
Socket 604 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
146mm² die
Xeon-2.0B MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
November 18, 2002 - {$198}
604 pins
2000MHz (133x15)
(64-bit quad-pumped bus)
1.5v
Socket 604 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
146mm² die
Xeon-2.2G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
February 25, 2002 - {$615}
603 pins
2200MHz (100x22)
(64-bit quad-pumped bus)
1.5v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
146mm² die
Xeon-2.4G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
April 23, 2002 - {$615}
603 pins
2400MHz (100x24)
(64-bit quad-pumped bus)
1.5v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
131mm² die
Xeon-2.4G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
November 18, 2002 - {$234}
604 pins
2400MHz (133x18)
(64-bit quad-pumped bus)
1.5v
Socket 604 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
131mm² die
Xeon-2.6G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
September 11, 2002 - {$433}
603 pins
2600MHz (100x26)
(64-bit quad-pumped bus)
1.5v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
131mm² die
Xeon-2.67G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
November 19, 2002 - {$337}
604 pins
2666MHz (133x20)
(64-bit quad-pumped bus)
1.5v
Socket 604 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
131mm² die
Xeon-2.8G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
September 11, 2002 - {$562}
603 pins
2800MHz (100x28)
(64-bit quad-pumped bus)
1.5v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
131mm² die
Xeon-2.8G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
November 18, 2002 - {$455}
604 pins
2800MHz (133x21)
(64-bit quad-pumped bus)
1.5v
Socket 604 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
131mm² die
Xeon-3.06G MMX SSE SSE2
(Prestonia)
(Jackson Hyperthreading Technology)
February 3, 2003 - {$722}
604 pins
3066MHz (133x23)
(64-bit quad-pumped bus)
1.5v
Socket 604 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
* 64GB cacheable
55 million
0.13痠 process
131mm² die
Xeon-3.06G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading Technology)
July 14, 2003 - {$690}
604 pins
3066MHz (133x23)
(64-bit quad-pumped bus)
1.525v
Socket 604 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable
169 million
0.13痠 process
~230mm² die
Xeon-3.2G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading Technology)
October 6, 2003 - {$851}
604 pins
3200MHz (133x24)
(64-bit quad-pumped bus)
1.525v
Socket 604 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable
169 million
0.13痠 process
~230mm² die
Xeon MP-1.5G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading Technology)
November 4, 2002 - {$1177}
603 pins
1500MHz (100x15)
(64-bit quad-pumped bus)
1.475v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable
169 million
0.13痠 process
~230mm² die
Xeon MP-1.9G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading Technology)
November 4, 2002 - {$1980}
603 pins
1900MHz (100x19)
(64-bit quad-pumped bus)
1.475v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable
169 million
0.13痠 process
~230mm² die
Xeon MP-2.0G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading Technology)
June 30, 2003 - {$1177}
603 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.475v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable
169 million
0.13痠 process
~230mm² die
Xeon MP-2.0G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading Technology)
November 4, 2002 - {$3692}
603 pins
2000MHz (100x20)
(64-bit quad-pumped bus)
1.475v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable
169 million
0.13痠 process
~230mm² die
Xeon MP-2.2G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading Technology)
2003?
603 pins
2200MHz (100x22)
(64-bit quad-pumped bus)
1.475v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB or
2MB on-Die L3 (8-way)
* 64GB cacheable
169 million
0.13痠 process
~230mm² die
Xeon MP-2.5G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading Technology)
June 30, 2003 - {$1980}
603 pins
2500MHz (100x25)
(64-bit quad-pumped bus)
1.475v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
1MB on-Die L3 (8-way)
* 64GB cacheable
169 million
0.13痠 process
~230mm² die
Xeon MP-2.8G MMX SSE SSE2
(Gallatin)
(Jackson Hyperthreading Technology)
June 30, 2003 - {$3692}
603 pins
2800MHz (100x28)
(64-bit quad-pumped bus)
1.475v
Socket 603 8KB data (4-way)
12k 發ps trace instruction (8-way)
512KB on-Die unified L2 (8-way)
2MB on-Die L3 (8-way)
* 64GB cacheable
169 million
0.13痠 process
~230mm² die
Xeon 3.2G MMX SSE SSE2
(Nocona)
4Q 2003?
? pins
3200MHz (133x24)
(64-bit quad-pumped bus)
?v
Socket ? ?KB data (?-way)
?k 發ps trace instruction (?-way)
1MB on-Die unified L2 (?-way)
* 64GB cacheable
? million
0.09痠 process
?mm² die
Xeon 3.47G MMX SSE SSE2
(Nocona)
4Q 2003?
? pins
3466MHz (133x26)
(64-bit quad-pumped bus)
?v
Socket ? ?KB data (?-way)
?k 發ps trace instruction (?-way)
1MB on-Die unified L2 (?-way)
* 64GB cacheable
? million
0.09痠 process
?mm² die
Xeon 3.5G MMX SSE SSE2
(Nocona)
1Q 2004?
? pins
3500MHz (166x21)
(64-bit quad-pumped bus)
?v
Socket ? ?KB data (?-way)
?k 發ps trace instruction (?-way)
1MB on-Die unified L2 (?-way)
* 64GB cacheable
? million
0.09痠 process
?mm² die
Xeon 3.6G MMX SSE SSE2
(Nocona)
2004?
? pins
3600MHz (133x27)
(64-bit quad-pumped bus)
?v
Socket ? ?KB data (?-way)
?k 發ps trace instruction (?-way)
1MB on-Die unified L2 (?-way)
* 64GB cacheable
? million
0.09痠 process
?mm² die
Xeon 3.67G MMX SSE SSE2
(Nocona)
1Q 2004?
? pins
3666MHz (166x22)
(64-bit quad-pumped bus)
?v
Socket ? ?KB data (?-way)
?k 發ps trace instruction (?-way)
1MB on-Die unified L2 (?-way)
* 64GB cacheable
? million
0.09痠 process
?mm² die
Xeon ? MMX SSE SSE2 SSE3
(Jayhawk)
(Jackson Hyperthreading Technology)
2H 2004?
? pins
?MHz (166x?)
(64-bit quad-pumped bus)
?v
Socket ? 24KB data (4-way)
16k 發ps trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable
? million
0.09痠 process
?mm² die
Xeon MP ? MMX SSE SSE2 SSE3
(Potomac)
(Jackson Hyperthreading Technology)
2004?
? pins
?MHz (166x?)
(64-bit quad-pumped bus)
?v
Socket ? 24KB data (4-way)
16k 發ps trace instruction (8-way)
1MB on-Die unified L2 (8-way)
* ?GB cacheable
? million
0.09痠 process
?mm² die
Goto  Top of Page..
Itanium (Merced)
Intel
Processors
Natural
State
Sockets L1/L2 Cache
(Associativity)
Transistors
Itanium-733 MMX SSE
(Merced)
July, 2001
418 pins
733MHz (133x5.5)
(64-bit dual-pumped bus)
?v
PAC418 16KB data (4-way)
16KB instruction (4-way)
96KB on-Die unified L2 (6-way)
2MB or
4MB unified L3 (4-way)
* 16TB cacheable
25 million
0.18痠 process
~300mm² die
? million L3 {?痠 - ?mm²} (2MB)
295 million L3 {?痠 - ?mm²} (4MB)
Itanium-800 MMX SSE
(Merced)
July, 2001
418 pins
800MHz (133x6.0)
(64-bit dual-pumped bus)
?v
PAC418 16KB data (4-way)
16KB instruction (4-way)
96KB on-Die unified L2 (6-way)
2MB or
4MB unified L3 (4-way)
* 16TB cacheable
25 million
0.18痠 process
~300mm² die
? million L3 {?痠 - ?mm²} (2MB)
295 million L3 {?痠 - ?mm²} (4MB)
Itanium 2-900 MMX SSE
(McKinley)
July 8, 2002 - {$1338} (1.5MB)
611 pins
900MHz (200x4.5)
(128-bit dual-pumped bus)
?v
PAC611 16KB data
16KB instruction
256KB on-Die unified L2
1.5MB on-Die unified L3
* ?GB cacheable
221 million
0.18痠 process
463mm² die
Itanium 2-1.0G MMX SSE
(McKinley)
July 8, 2002 - {$?} (1.5MB)
July 8, 2002 - {$4226} (3MB)
611 pins
1000MHz (200x5.0)
(128-bit dual-pumped bus)
?v
PAC611 16KB data
16KB instruction
256KB on-Die unified L2
1.5MB or
3MB on-Die unified L3
* ?GB cacheable
221 million
0.18痠 process
463mm² die
Itanium 2-1.3G MMX SSE
(Madison) - copper chip
June 30, 2003 - {$1338}
611 pins
1300MHz (200x6.5)
(128-bit dual-pumped bus)
?v
PAC611 16KB data
16KB instruction
256KB on-Die unified L2
3MB on-Die unified L3
* ?GB cacheable
~500 million
0.13痠 process
?mm² die
Itanium 2-1.4G MMX SSE
(Madison) - copper chip
June 30, 2003 - {$2247}
611 pins
1400MHz (200x7.0)
(128-bit dual-pumped bus)
?v
PAC611 16KB data
16KB instruction
256KB on-Die unified L2
4MB on-Die unified L3
* ?GB cacheable
~500 million
0.13痠 process
?mm² die
Itanium 2-1.5G MMX SSE
(Madison) - copper chip
June 30, 2003 - {$3692}
611 pins
1500MHz (200x7.5)
(128-bit dual-pumped bus)
?v
PAC611 16KB data
16KB instruction
256KB on-Die unified L2
6MB on-Die unified L3
* ?GB cacheable
~500 million
0.13痠 process
?mm² die
LV Itanium 2-1.0G MMX SSE
(Deerfield)
September 8, 2003 - {$744}
611 pins
1000MHz (200x5.0)
(128-bit dual-pumped bus)
?v
PAC611 16KB data
16KB instruction
256KB on-Die unified L2
1.5MB on-Die unified L3
* ?GB cacheable
? million
0.13痠 process
?mm² die
Itanium 2-1.4G MMX SSE
(Deerfield)
September 8, 2003 - {$1172}
611 pins
1400MHz (200x7.0)
(128-bit dual-pumped bus)
?v
PAC611 16KB data
16KB instruction
256KB on-Die unified L2
1.5MB on-Die unified L3
* ?GB cacheable
? million
0.13痠 process
?mm² die
Itanium 2 MMX SSE
(Deerfield)
2H 2003?
611 pins
?MHz (200x?)
(128-bit dual-pumped bus)
?v
PAC611 16KB data
16KB instruction
256KB on-Die unified L2
3MB on-Die unified L3
* ?GB cacheable
? million
0.13痠 process
?mm² die
Itanium 2 MMX SSE
(Madison 9M)
2H 2003?
611 pins
?MHz (200x?)
(128-bit dual-pumped bus)
?v
PAC611 16KB data
16KB instruction
256KB on-Die unified L2
3MB on-Die unified L3
* ?GB cacheable
? million
?痠 process
?mm² die
Itanium 2 MMX SSE
(Montecito)
(Jackson Hyperthreading Technology)
2005?
611 pins
?MHz (?x?)
(128-bit dual-pumped bus)
?v
PAC611 ?KB data
?KB instruction
?KB on-Die unified L2
?MB on-Die unified L3
* ?GB cacheable
? million
0.09痠 process
?mm² die
Itanium 2 MMX SSE
(Shavano)
(Jackson Hyperthreading Technology)
2005?
? pins
?MHz (?x?)
(128-bit dual-pumped bus)
?v
? ?KB data
?KB instruction
?KB on-Die unified L2
?MB on-Die unified L3
* ?GB cacheable
? million
?痠 process
?mm² die
Itanium 2 MMX SSE
(Tanglewood)
(Jackson Hyperthreading Technology)
2006?
? pins
?MHz (?x?)
(?-bit ?-pumped bus)
?v
? ?KB data
?KB instruction
?KB on-Die unified L2
?MB on-Die unified L3
* ?GB cacheable
? million
?痠 process
?mm² die
Goto  Top of Page..
Athlon 64
AMD
Processors
Natural
State
Sockets L1/L2 Cache
(Associativity)
Transistors
Athlon 64-??? MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC2700 mem controller; 4GB max)
754 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v
Socket 754 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
? million
0.13痠 process
104mm² die
Athlon 64-3200+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
September 23, 2003 - {$417}
754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v
Socket 754 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Athlon 64-3400+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
2004?
754 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v
Socket 754 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Athlon 64-4000+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
2004?
754 pins
?MHz (200x?)
(64-bit dual-pumped bus)
1.5v
Socket 754 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Athlon 64-??? MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
2004?
754 pins
?MHz (200x?)
(64-bit dual-pumped bus)
1.5v
Socket 754 64KB data (2-way)
64KB instruction (2-way)
?KB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
? million
0.13痠 process
?mm² die
Athlon 64-??? MMX 3DNow! SSE SSE2
(San Diego)
(64-bit on-Die unbuffered DDR-II mem controller)
754 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v
Socket 754 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
? million
0.09痠 process
64mm² die
Athlon 64-4400 MMX 3DNow! SSE SSE2
(San Diego)
(64-bit on-Die unbuffered DDR-II mem controller)
2004?
754 pins
?MHz (200x?)
(64-bit dual-pumped bus)
1.5v
Socket 754 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
? million
0.09痠 process
~120mm² die
Athlon 64-??? MMX 3DNow! SSE SSE2
(Victoria)
(64-bit on-Die unbuffered DDR-II mem controller)
2004?
754 pins
?MHz (200x?)
(64-bit dual-pumped bus)
1.5v
Socket 754 64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
? million
0.09痠 process
?mm² die
Athlon 64 FX-51 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
September 23, 2003 - {$733}
940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Athlon 64 FX-53 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
2003?
940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Athlon 64 FX-??? MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
1Q 2004?
939 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v
Socket 939 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Goto  Top of Page..
Opteron
AMD
Processors
Natural
State
Sockets L1/L2 Cache
(Associativity)
Transistors
Opteron-??? MMX 3DNow! SSE SSE2
(Clawhammer DP)
(128-bit on-Die DDR PC2700 mem controller; 8GB max)
2003?
940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
? million
0.13痠 process
104mm² die
Opteron-140 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$229}
940 pins
1400MHz (200x7.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-142 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$438}
940 pins
1600MHz (200x8.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-144 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$669}
940 pins
1800MHz (200x9.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-146 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
September 9, 2003 - {$669}
940 pins
2000MHz (200x10.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-240 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
April 22, 2003 - {$283}
940 pins
1400MHz (200x7.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-242 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
April 22, 2003 - {$690}
940 pins
1600MHz (200x8.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-244 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
April 22, 2003 - {$794}
940 pins
1800MHz (200x9.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-246 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
August 5, 2003 - {$794}
940 pins
2000MHz (200x10.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-2XX MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
2003?
940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-840 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$749}
940 pins
1400MHz (200x7.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-842 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$1299}
940 pins
1600MHz (200x8.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-844 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
June 30, 2003 - {$2149}
940 pins
1800MHz (200x9.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-846 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
September 9, 2003 - {$3199}
940 pins
2000MHz (200x10.0)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-8XX MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
2003?
940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
1.55v
Socket 940 64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
106 million
0.13痠 process
193mm² die
Opteron-??? MMX 3DNow! SSE SSE2
(Athens)
(128-bit on-Die registered DDR PC2700 mem controller; 8GB max)
1H 2003?
940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v
Socket ? 64KB data (2-way)
64KB instruction (2-way)
?MB on-Die unified L2 (16-way exclusive)
* ?GB cacheable
? million
0.09痠 process
?mm² die
Goto  Top of Page..

Notes:

  • Technically not all the CPUs listed here qualify as "7th Generation" processors, but the 586/686 page was getting rather large.
  • - micron (millionth of a meter).
  • The dates listed are official introduction dates. It does not necessarily mean those processors were available in quantity on that date. Processor names that are italicized in green indicate a tentative release date based on various news articles, speculation, and sometimes pure rumor.
  • The prices listed with each processor are its price at the chip's introduction in US dollars. Except for the OverDrive chips, all prices are for quantities of 1000.
  • All bus speeds listed on this page are actual speeds; not DDR. The Athlon, Willamette, Foster, and Merced chips all use a dual (2x) or quad-pumped (4x) bus that hits on the rising and falling edges of the clock, yielding a faster effective bus speed. The quad-pumped bus works similar to that of AGP 4x mode (it uses a synchronous signal to double strobe each rising and falling edge).
  • The Athlon XP Thoroughbred chip comes in two different core sizes: 81mm² (6-8-0 step) and 84mm² (6-8-1 step).

 

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